I am leading the modernization of Rodinia for CUDA 12+, larger datasets, and contemporary GPU features such as Tensor Cores, Cooperative Groups, and multi-GPU. I built a reproducible harness to compare legacy versus modernized implementations across GPU generations and created microbenchmarks that isolate memory hierarchy, warp scheduling, and synchronization effects. Using Nsight tooling and GPGPU-Sim, I focus on making results explainable so architectural choices map cleanly to application-level behavior.

Presentation: University of Virginia - Undergraduate Engineering Research and Design Symposium, Charlottesville, VA (Expected April 2026)

I simulated extended L2 cache designs in GPGPU-Sim and co-modeled area and latency with CACTI to study bandwidth-latency trade-offs, hit-rate impacts, and workload sensitivity. I evaluated design points with Rodinia and ML kernels, scripted parameter sweeps, and analyzed how cache capacity and organization shape end-to-end performance. This study complements my benchmark modernization by tying memory-system choices to observed kernel behavior.

Presentation: University of Virginia Engineering Research Expo, Charlottesville, VA (November 2025)

I developed an iterative optimization pipeline using LLM-based prompting to accelerate GPT-4o-generated CUDA code, documenting recurring bottlenecks and best practices for LLM-assisted GPU programming. I profiled and compared LLM-optimized CUDA against PyTorch implementations on NVIDIA H100/A100 GPUs, revealing framework trade-offs for ML workload selection. Additionally, I stress-tested large-scale models (ResNet-50, BERT) with RAPIDS AI libraries (cuML, cuDF, TensorRT) to assess scalability and performance across different optimization strategies.

Presentations:
• University of Virginia - Undergraduate Engineering Research and Design Symposium, Charlottesville, VA (April 2025)
• University of Virginia Engineering Research Expo, Charlottesville, VA (October 2024)

I reproduced the MLPerf v4.0 ResNet-50 Training benchmark on UVA GPU servers, identifying throughput bottlenecks and tuning multi-GPU NVLink scaling with mixed-precision Tensor Cores and XLA. I am currently comparing MLPerf Training/Inference with MLPerf Tiny to characterize scaling inefficiencies between edge deployments and large-scale GPU clusters.

I built a GPU reproducible MD workflow for entropy-stabilized oxides using GPUMD and a Neuroevolution ML Potential. Additionally, I automated large simulation batches with SLURM job arrays, improved NEP training on GPUs to reduce energy and force error, and analyzed thermal trends across temperatures and compositions. The project lead to a Journal of Applied Physics publication and seeded my interest in the hardware–software interface, especially GPU computing that ultimately drives performance.

Presentation: University of Virginia Research Computing Exhibition, Charlottesville, VA (April 2025)

I modeled extended GPU L2 cache architectures in GPGPU-Sim using memory-bound Rodinia benchmarks (BFS, K-means, Gaussian Elimination, Needleman–Wunsch) to evaluate cache behavior under realistic workloads. I evaluated trade-offs between larger L2 capacity, higher associativity, and prefetching, pinpointing configurations where extra cache lowers miss rates and runtime without prohibitive area or energy overheads.

I designed and tuned multiple CUDA kernels for SpMSpM using shared-memory hashing and dynamic scheduling across NVIDIA GPUs to balance parallelism, occupancy, and memory traffic, achieving significant speedups over CPU baselines by exploiting GPU memory hierarchies and warp-level operations. The project involved profiling with Nsight Compute to identify bottlenecks and iteratively optimizing for different matrix sizes and sparsity levels.

I explored CPU/GPU memory hierarchies, cache modeling, DRAM simulation, CUDA programming, and near-data processing using PIMeval-PIMbench to build intuition for memory-centric architectures.